In the simultaneous conversion method of converting an analog voltage to a digital representation, all bits of the digital representation are determined simultaneously. This method is also known as the parallel method because the conventional implementation of this method has a parallel bank of voltage comparators, each comparator being responsive to the analog voltage attaining a predetermined voltage level.
In an N-bit encoder where N is a predetermined integer, there are exactly 2.sup.N digital output states. A maximum analog voltage is divided into 2.sup.N voltage levels. Each level represents a quantum of voltage and each quantum level is represented by one of the digital output states. Conventional N-bit encoders require 2.sup.N comparators; that is, each comparator determines the transition to a unique quantum level. Thus, conventional parallel implementation of the simultaneous conversion method requires a prohibitive number of comparators if N is large. In practice, one disadvantage is that the number of comparators becomes prohibitive when N is six (6) or greater. However, the ultra high-speed conversion possible with this method makes overcoming this disadvantage highly desirable.
Another disadvantage of the simultaneous conversion method is that the output from the parallel bank of voltage comparators is in the form of 2.sup.N -1 binary data signals rather than in a compact format. Conventionally, the 2.sup.N -1 outputs are further encoded to N bits of binary information in some compact binary format by conversion logic. For large values of N, typically six (6) or greater, the number of elements required in the conversion logic becomes prohibitively large because of the large number of inputs and logic combinations which must be provided for.
Thus, in the prior art, the high-speed conversion of the simultaneous conversion method, also known as "flash encoding", is not realizable for encoders characterized by high values of N because of the prohibitively large number of comparators required and the complexity of the conversion logic.